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this is information on a product in full production. march 2012 doc id 022817 rev 2 1/65 65 L6360 io-link communication master transceiver ic datasheet ? production data features supply voltage from 18 to 32.5 v programmable output stages: high-side, low-side or push-pull (< 2 ) up to 500 ma l+ protected high-side driver supports com1, com2 and com3 mode additional iec61131-2 type-1 input short-circuit and overcurrent output protection through current limitation and programmable cutoff current 3.3 v / 5 v, 50 ma linear regulator 5 ma io-link digital input fast mode i 2 c for ic control, configuration and diagnostic diagnostic dual led sequence generator and driver 5 v and 3.3 v compatible i/os overvoltage protection (> 36 v) overtemperature protection esd protection miniaturized: vfqfpn-26l 3.5 x 5 x 1 mm package applications industrial sensors factory automation process control description the L6360 is a monolithic io-link master port compliant with phy2 (3 wires) supporting com1 (4.8 kbaud), com2 (38.4 kbaud) and com3 (230.4 kbaud) modes. the c/q o output stage is programmable: high- side, low-side or push-pull; also cutoff current, cutoff current delay time, and restart delay are programmable. cutoff current and cutoff current delay time, combined with thermal shutdown and automatic restart protect the device against overload and short-circuit. c/q o and l+ output stages are able to drive resistive, inductive and capacitive loads. inductive loads up to 10 mj can be driven. supply voltage is monitored and low voltage conditions are detected. the L6360 transfers, through the phy2(c/q o pin), data received from a host microcontroller through the usart (in c/q o pin), or to the usart (out c/q i pin) data received from phy2 (c/q i pin). to enable full ic control, configuration and monitoring (i.e. fault conditions stored in the status register), the communication between the system microcontroller and the L6360 is based on a fast mode 2-wire i 2 c. the L6360 has nine registers to manage the programmable parameters and the status of the ic. monitored fault conditions are: l+ line, overtemperature, c/q overload, linear regulator undervoltage, and parity check. internal led driver circuitries, in open drain configuration, provide two programmable sequences to drive two leds. vfqfpn-26l 3.5 x 5 x 1 mm www.st.com www.datasheet.net/ datasheet pdf - http://www..co.kr/
contents L6360 2/65 doc id 022817 rev 2 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 i2c single master bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.4 sda/scl line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.5 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1.7 communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.8 i 2 c address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.9 internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.10 startup default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3 demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3.1 fast demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3.2 slow demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.4 i 2 c protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.4.1 protocol configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.4.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7 physical layer communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.1 transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.2 iec 61131-2 type 1 digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 contents doc id 022817 rev 2 3/65 8 diagnostic led seque nce generator and driver . . . . . . . . . . . . . . . . . 55 9 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11 emc protection considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.1 supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.2 i/o lines protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 www.datasheet.net/ datasheet pdf - http://www..co.kr/
contents L6360 4/65 doc id 022817 rev 2 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. electrical characteristics - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. electrical characteristics - linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. electrical characteristics - logic inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. electrical characteristics - led driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. electrical characteristics - i 2 c (fast mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. main parameters typical variation vs. +/- 1% variation of r bias value . . . . . . . . . . . . . . . . . 17 table 12. register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. en cgq : c/q pull-down enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. i coq : c/q o hs and ls cutoff current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. t dcoq : c/q o hs and ls cutoff current delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 16. t rcoq : c/q o restart delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17. t dbq : c/q i de-bounce time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 18. en cgi : i/q pull-down enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 19. cq pdg : c/q pull-down generator switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 20. l+ cod : l+ cutoff disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 21. t dcol : l+ hs cutoff current delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 22. t rcol : l+ restart delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 table 23. t dbi : i/q de-bounce time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 24. c/q output stage configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 25. parameters default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 26. registers default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 27. current write mode direction bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 28. sequential write mode direction bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 29. read mode: register address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 30. address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 31. linear regulator selection pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 32. supply voltage protection component description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 33. refined supply voltage protection component description . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 34. v h protection component description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 35. typical protection in io-link applications component description . . . . . . . . . . . . . . . . . . . 61 table 36. io-link and sio applications extended protection component description . . . . . . . . . . . . 62 table 37. mechanical data for vfqfpn - 26-lead 3.5 x 5 x 1 mm - 0.50 pitch . . . . . . . . . . . . . . . . . 63 table 38. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 list of figures doc id 022817 rev 2 5/65 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. rise/fall time test setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. normalized rise and fall time vs. output capacitor value (typ. values in push-pull configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. a master transmitter addressing a slave receiver with a 7-bit address (the transfer is not changed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. a master reads data from the slave immediately after the first byte . . . . . . . . . . . . . . . . . . 19 figure 7. transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. i 2 c communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. power-on bit behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11. overtemperature (ovt) bit behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12. cutoff behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 13. control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 14. control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 15. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 16. led1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17. led2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 18. parity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 19. power stage. q2 is not present on l+ output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 20. fast demagnetization principle schematic. load connected to l- . . . . . . . . . . . . . . . . . . . 38 figure 21. fast demagnetization waveform. load connected to l- . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 22. slow demagnetization schematic block. load connected to l- . . . . . . . . . . . . . . . . . . . . . 39 figure 23. slow demagnetization waveform. load connected to gnd . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 24. device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 25. current write mode flow chart procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 26. current write mode frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 27. sequential write mode flow chart procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 28. sequential write mode frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 29. microcontroller parity check calculus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 30. register sequence in sequential write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 31. current read mode flow chart procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 32. current read mode frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 33. current read communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 34. sequential/random read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 35. sequential/random read communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 36. block diagram communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 37. system communication mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 38. c/q or l+ channel cutoff protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 39. c/q or l+ channel current limitation and cutoff protection with latched restart . . . . . . . . . 54 figure 40. led drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 41. linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 42. linear regulator principle schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 43. application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 44. supply voltage protection with uni-directional transil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 45. refined supply voltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 46. v h protection vs. v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 www.datasheet.net/ datasheet pdf - http://www..co.kr/
list of figures L6360 6/65 doc id 022817 rev 2 figure 47. typical protection in io-link applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 48. io-link and sio applications extended protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 49. package outline for vfqfpn - 26-lead 3.5 x 5 x 1 mm - 0.50 pitch . . . . . . . . . . . . . . . . . . 63 www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 block diagram doc id 022817 rev 2 7/65 1 block diagram figure 1. block diagram table 1. device summary ,).%!22%'5,!4/2 ) # ).4%2&!#% #/.&)'52!4)/.#/.42/,$)!'./34)# ,%$s #/.42/, ")!3 #onfig digital filter 6 ## , #1 ) #1 / , )1 5.$%2 6/,4!'% 6 $$ 3%, 6 ( 2 bias #onfig digital filter /6%2 4%-0%2!452% 02/4%#4)/. $)')4!, ).4%2&!#% ,%$ ,%$ 3! 3! 3! )21 234 3#, 3$! /54 )1 /54 #1 ). #1 %. #1 %. , !- order code package packaging L6360 vfqfpn 3.5 x 5 x 1 - 26 leads tray L6360tr vfqfpn 3.5 x 5 x 1 - 26 leads tape and reel www.datasheet.net/ datasheet pdf - http://www..co.kr/
pin connections L6360 8/65 doc id 022817 rev 2 2 pin connections figure 2. pin connections (top view) table 2. pin description pin name description type 1v cc ic power supply supply 2 l- l- line (ic ground) supply 3v h linear regulator supply voltage supply 4v dd linear regulator output voltage output 5 sa1 serial address 1 input 6 sa2 serial address 2 input 7r bias external resistor for internal reference generation input 8 sel linear regulator 3.3 v/5 v voltage selection. output is 5 v when sel pin is pulled to gnd. input 9en c/q c/q output enable input 10 in c/q c/q channel logic input input 11 out c/q c/q channel logic output output 12 out i/q i/q channel logic output output !- 6 ## , 6 ( 6 $$ 3! 3! 2 bias 3%, , ,%$ ,%$ 3! 234 3$! 3#, )21 #1 / #1 ) )1 , 6 ## %. #1 ). #1 /54 #1) /54 )1 %. , www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 pin connections doc id 022817 rev 2 9/65 13 en l+ l+ switch enable. when en l+ is high the switch is closed input 14 irq interrupt request signal (open drain) output 15 scl serial clock line input 16 sda serial data line input/output 17 rst reset - active low input 18 sa0 serial address 0 input 19 led1 status/diagnostic led (open drain) output 20 led2 status/diagnostic led (open drain) output 21 l- l- line (ic ground) supply 22 v cc ic power supply supply 23 l+ l+ line supply 24 i/q i/q channel line input 25 c/q i transceiver (c/q channel) line input 26 c/q o transceiver (c/q channel) line output table 2. pin description (continued) pin name description type www.datasheet.net/ datasheet pdf - http://www..co.kr/
absolute maximum ratings L6360 10/65 doc id 022817 rev 2 3 absolute maximum ratings table 3. absolute maximum ratings symbol parameter value unit v cc supply voltage v clamp v v sel linear regulator selection pin voltage -0.3 to 4 v v dd linear regulator output voltage 5.5 v v h linear regulator input voltage v cc v v inc/q , enc/q , enl+ in c/q , en c/q , en l+ voltage -0.3 to v dd + 0.3 v v sda , scl , sa0 , 1 , 2 i 2 c voltage -0.3 to v dd + 0.3 v v led1 , 2 led1, 2 voltage -0.3 to v dd + 0.3 v v c/qi , v i/q c/q i , i/q voltage -0.3 to v cc + 0.3 v v rst reset voltage -0.3 to v dd + 0.3 v v irq irq voltage -0.3 to v dd + 0.3 v v rbias external precision resistance voltage -0.3 to 4 v v esd electrostatic discharge (human body model) 2000 v i clamp current through v clamp in surge test (1 kv, 500 ) condition 2 a i c/qo , i l+ c/q o , l+ current (continuous) internally limited a i outc//q , i outi/q out c/q , out i/q output current 5 ma i sda i 2 c transmission data current (open drain pin) 10 ma i irq interrupt request signal current 10 ma i led1 , 2 led1, 2 current 10 ma e load l+ demagnetization energy 10 mj p tot power dissipation at t c = 25 c internally limited w p lr linear regulator power dissipation 200 mw t j junction operating temperature internally limited c t stg storage temperature -55 to 150 c www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 recommended operating conditions doc id 022817 rev 2 11/65 4 recommended operating conditions table 5. thermal data table 4. recommended operating conditions symbol parameter test condition min. typ. max. unit v cc supply voltage - 18 32.5 v v h linear regulator input voltage 7 v cc v f scl scl clock frequency 400 khz r bias precision resistance -0.1% 124 0.1% k t j junction temperature -25 125 c symbol parameter typ. unit r th j-case thermal resistance, junction-to-case 6 c/w r th j-amb thermal resistance, junction-to-ambient (1) 1. mounted on fr4 pcb with 2 signal cu layers and 2 power cu layers interconnected through vias. 50 c/w www.datasheet.net/ datasheet pdf - http://www..co.kr/
electrical characteristics L6360 12/65 doc id 022817 rev 2 5 electrical characteristics (18 v < v cc < 30 v; -25 c < t j < 125 c; v dd = 5 v; unless otherwise specified.) xxx table 6. electrical characteristics - power section symbol parameter test condition min. typ. max. unit v clamp voltage clamp i = 5 ma 36 v v uv undervoltage on-threshold 16 17 18 v v uvh undervoltage hysteresis 0.3 1 v v regln5h linear regulator undervoltage high threshold sel = l 4.3 4.7 v v regln5l linear regulator undervoltage low threshold sel = l 3.6 4.2 v v reg5hys linear regulator undervoltage hysteresis sel = l 0.1 v v regln33h linear regulator undervoltage high threshold sel = h 2.8 3.1 v v regln33l linear regulator undervoltage low threshold sel = h 2.5 2.7 v v reg33hys linear regulator undervoltage hysteresis sel = h 0.1 v v qthh c/q i and i/q upper voltage threshold 10.5 12.9 v v qthl c/q i and i/q lower voltage threshold 8 11.4 v v qhy c/q and i/q hysteresis voltage 1 v v demag l+ demagnetization voltage i = 5 ma -8.5 -6.5 -4.8 v v fhs c/q high-side freewheeling diode forward voltage i = 10 ma 0.5 v v fls c/q low-side freewheeling diode forward voltage i = 10 ma 0.5 v v lth of f l+ line diagnostic lower threshold 9 10 11 v v lth y l+ line diagnostic hysteresis 0.1 1 v v lth on l+ line diagnostic upper threshold 10 11 12 v i s supply current off-state 100 a on-state v cc at 32.5 v 4 ma i offcq off-state c/q o current en c/q = 0, v c/q = 0 v 1 a i coq c/q o low- and high-side cutoff current programmable (see control register 1 ) 70 115 190 ma 150 220 300 ma 290 350 440 ma 430 580 720 ma www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 electrical characteristics doc id 022817 rev 2 13/65 i limq c/q o low- and high-side limitation current 500 1600 ma i offl l+ off-state current en l+ = 0, v l+ = 0 v 0 200 a i col l+ cutoff current 480 580 730 ma i liml l+ limitation current 500 1600 ma i inc/qi c/q i pull-down current programmable (see section control register 2 ) 56.5ma 23.3ma i ini/q i/q pull-down current (see control register 2 )2 3ma r onl l+ high-side on-state resistance i out = 0.2 a at t j = 25 c 1 i out = 0.2 a at t j = 125 c 2 r oncqh c/q o high-side on-state resistance i out = 0.2 a at t j = 25 c 1 i out = 0.2 a at t j = 125 c 2 r oncql c/q o low-side on-state resistance i out = 0.2 a at t j = 25 c 0.6 i out = 0.2 a at t j = 125 c 1.2 t dinc/q in c/q to c/q o propagation delay time push-pull (cq o rising edge) 140 ns push-pull (cq o falling edge) 160 ns t enc/q en c/q to c/q o propagation delay time push-pull (cq o rising edge) 110 ns push-pull (cq o falling edge) 225 ns t rpp c/q rise time in push-pull configuration 10% to 90%. see figure 3 250 860 ns t fpp c/q fall time in push-pull configuration 10% to 90%. see figure 3 290 860 ns t rhs c/q rise time in high-side configuration 410 ns t fhs c/q fall time in high-side configuration 700 ns t rls c/q rise time in low-side configuration 750 ns t fls c/q fall time in low-side configuration 530 ns t enl en l to l+ propagation delay time 1 s t rl+ l+ rise time 3 s t fl+ l+ fall time 25 s t dc/qi c/q i to out c/q (falling) propagation delay time 40 ns c/q i to out c/q (rising) propagation delay time 100 ns t di/q i/q to out i/q (falling) propagation delay time 40 ns i/q to outi /q (rising) propagation delay time 100 ns table 6. electrical characteristics - power section (continued) symbol parameter test condition min. typ. max. unit www.datasheet.net/ datasheet pdf - http://www..co.kr/
electrical characteristics L6360 14/65 doc id 022817 rev 2 t dcoq c/q o low- and high-side cutoff current delay time programmable (see control register 1 ) 100 s 150 s 200 s 250 s t rcoq c/q o restart delay time programmable (see control register 1 ) 255 t dcoq latched (1) t dbq c/q i de-bounce time programmable (see control register 1 ) 0s 5s 20 s 100 s t dbl i/q de-bounce time programmable (see control register 2 ) 0s 5s 20 s 100 s t dcol l+ cutoff current delay time programmable (see control register 2 ) 500 s 0s t rcol l+ restart delay time programmable (see control register 2 ) 64 ms latched (1) t jsd junction temperature shutdown 150 c t jhyst junction temperature thermal hysteresis 20 c t jrst junction temperature restart threshold 130 c 1. unlatch through i 2 c communication. table 6. electrical characteristics - power section (continued) symbol parameter test condition min. typ. max. unit www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 electrical characteristics doc id 022817 rev 2 15/65 table 8. electrical characteristics - logic inputs and outputs table 7. electrical characteristics - linear regulator symbol parameter test condition min. typ. max. unit v dd linear regulator output voltage sel = l 4.84 5 5.13 v sel = h 3.22 3.3 3.37 v i limlr linear regulator output current limitation 65 ma symbol parameter test condition min. typ. max. unit v il input low-level voltage 0.8 v v ih input high-level voltage 2.2 v v ihis input hysteresis voltage 0.2 v i in input current v in = 5 v 1 a v ol output low-level voltage i out = -2 ma 0.5 v v oh output high-level voltage i out = 2 ma v dd - 0.5 v v v lirq open drain output low-level voltage i out = 2 ma 0.5 v table 9. electrical characteristics - led driving symbol parameter test condition min. typ. max. unit v led1 , 2 open drain output low-level voltage i led = 2 ma - 0.5 v i led led1, 2 leakage current v led1 = v led2 = 5 v 3 na table 10. electrical characteristics - i 2 c (fast mode) (1) symbol parameter test condition min. max. unit v il(sda) sda low-level input voltage 0.3 v v ih(sda) sda high-level input voltage 0.7 x v dd v v il(scl) scl low-level input voltage 0.3 v v ih(scl) scl high-level input voltage 0.7 x v dd v i in i 2 c sda, scl input current (0.1 x v dd ) electrical characteristics L6360 16/65 doc id 022817 rev 2 figure 3. rise/fall time test setup figure 4. normalized rise and fall time vs. output capacitor value (typ. values in push-pull configuration) t su(sta) repeated start condition setup 0.6 s t su(sto) stop condition setup time 0.6 s t w(start/stop) stop to start condition time (bus free) 1.3 s t w(scll) scl clock low time 1.3 s t w(sclh) scl clock high time 0.6 s c b capacitance for each bus line 400 pf c i capacitance for each i/o pin 10 pf 1. values based on standard i 2 c protocol requirement. table 10. electrical characteristics - i 2 c (fast mode) (1) (continued) symbol parameter test condition min. max. unit n& n& #1 / , !- t 200 t &00 #n& !- www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 electrical characteristics doc id 022817 rev 2 17/65 table 11. main parameters typical variation vs. +/- 1% variation of r bias value symbol parameter typ. variation vs. r bias r bias [k ] 122.74 124 125.24 i s supply current 0.76% 0 -0.50% i inc/qi input current c/q i pin (5.5 ma) 0.93% 0 -0.93% i inc/qi input current c/q i pin (2.5 ma) 0.75% 0 -1.13% i ini/q input current i/q pin (2.5 ma) 0.85% 0 -0.85% t dcoq c/q o low- and high-side cutoff current delay time -2.44% 0 2.00% i coq c/q o low- and high-side cutoff current (115 ma) 1.19% 0 -1.28% t dcol l+ cutoff current delay time (500 s) -0.95% 0 0.47% i col l+ cutoff current 1.36% 0 -0.91% t rcol l+ restart delay time -0.93% 0 0.97% v uv undervoltage on-threshold 0.00% 0 0.00% v dd linear regulator output voltage (3.3 v) -0.03% 0 0.03% v dd linear regulator output voltage (5 v) -0.02% 0 0.02% i limq c/q o high-side limitation current 0.64% 0 -0.71% i limq c/q o low-side limitation current 0.28% 0 -1.47% i liml l+ limitation current 0.47% 0 -2.09% v qthh c/q i and i/q upper voltage threshold 0.00% 0 0.00% v qthl c/q i and i/q lower voltage threshold 0.00% 0 0.00% v qhy c/q and i/q hysteresis voltage 0.00% 0 0.00% t rpp c/q rise time in push-pull configuration -1.59% 0 1.18% t fpp c/q fall time in push-pull configuration -2.14% 0 0.94% t dinc/q i nc/q to c/q o propagation delay time -1.44% 0 0.75% t dinc/q in c/q to c/q o propagation delay time -2.36% 0 0.18% t dc/qi c/q i to out c/q propagation delay time 0.49% 0 1.13% t dc/qi c/q i to out c/q propagation delay time 1.82% 0 0.03% t dbq c/q i de-bounce time (100 s) -1.76% 0 1.50% t dcoq c/q o low- and high-side cutoff current delay time (200 s) -1.27% 0 2.00% i coq c/q o low-side cutoff current (220 ma) 0.39% 0 -1.56% i coq c/q o low-side cutoff current (350 ma) 0.36% 0 -1.43% i coq c/q o low-side cutoff current (580 ma) 0.65% 0 -1.72% t rcoq c/q o restart delay time -0.90% 0 0.97% i coq c/q o high-side cutoff current (220 ma) 0.84% 0 -0.84% i coq c/q o high-side cutoff current (350 ma) 1.38% 0 -0.69% i coq c/q o high-side cutoff current (580 ma) 1.08% 0 -1.08% www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 18/65 doc id 022817 rev 2 6 device configuration sda and scl configure the L6360 device through i 2 c. 6.1 i2c single master bus interface 6.1.1 introduction the i 2 c bus interface serves as an interface between the microcontroller and the serial i 2 c bus. it provides single master functions, and controls all i 2 c bus-specific sequencing, protocol and timing. it supports fast i 2 c mode (400 khz). 6.1.2 main features parallel bus / i 2 c protocol converter interrupt generation fast i 2 c mode 7-bit addressing. 6.1.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa. the interface is connected to the i 2 c bus by a data pin (sda) and a clock pin (scl). 6.1.4 sda/scl line control sda is a bi-directional line, scl is the clock input. sda should be connected to a positive supply voltage via a current-source or pull-up resistor. when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open drain or open collector output to perform the wired and function. data on the i 2 c bus can be transferred at rates up to 400 kbit/s in fast mode. the number of interfaces connected to the bus is limited by the bus capacitance. for a single master application, the master's scl output can be a push-pull driver provided that there are no devices on the bus which would stretch the clock. transmitter mode: the microcontroller interface holds the clock line low before transmission. receiver mode: the microcontroller interface holds the clock line low after reception. when the i 2 c microcontroller cell is enabled, the sda and scl ports must be configured as floating inputs. in this case, the value of the external pull-up resistors used depends on the application. www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 19/65 when the i 2 c microcontroller cell is disabled, the sda and scl ports revert to being standard i/o port pins. on the L6360, the sda output is an open drain pin. 6.1.5 mode selection possible data transfer formats are: the master transmitter transmits to the slave receiver. the transfer direction is not changed (see figure 5 ). the slave receiver acknowledges each byte. the master reads data from the slave immediately after the first byte (see figure 6 ). at the moment of the first acknowledge, the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. this first acknowledge is still generated by the slave. subsequent acknowledges are generated by the master. the stop condition is generated by the master which sends a not-acknowledge (a ) just prior to the stop condition. figure 5. a master transmitter addressing a slave receiver with a 7-bit address (the transfer is not changed) figure 6. a master reads data from the slave immediately after the first byte 3, !6%!$$2%33 27 ! $!4! !.! ! $!4! @ write $atatransferred nbyte sacknowledge frommastertoslave fr omslavetomaster ! ac knowledge 3$! ,/7 .! notacknowledge3$!()'( 3 34!24c ondition 0 34/0condition 3 , ! 6 % !$ $2 % 33 2 7 $! 4 ! $!4! !- 3 0 3,!6% !$$2%33 27 ! $!4! !.! ! $!4! @ read $atatransferred nbyte sacknowledge 3 ,!6 % !$$2% 33 2 7 ! .! ! frommaster toslave fr omslavetomaster ! acknowledge 3$! ,/7 .! notac knowledge3$! ()'( 3 34!24 condition 0 34/0condit ion !- 3 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 20/65 doc id 022817 rev 2 on the microcontroller, the interface can operate in the two following modes: master transmitter/receiver idle mode (default state) the microcontroller interface automatically switches from idle to master receiver after it detects a start condition and from master receiver to idle after it detects a stop condition. on the L6360 the interface can operate in the two following modes: slave transmitter/receiver idle mode (default state) the interface automatically switches from idle to slave transmitter after it detects a start condition and from slave transmitter to idle after it detects a stop condition. 6.1.6 functional description by default, the i 2 c microcontroller interface operates in idle; to switch from default idle mode to master mode a start condition generation is needed. the transfer sequencing is shown in figure 7 . figure 7. transfer sequencing !- 3 3,!6%!$$2%33 27 ! $!4! !.! ! $!4! . 0 x 3 3,!6%!$$2%33 27 ! $!4 ! !.! ! $!4! . 0 x bit master receiver microcontroller slave transmitter , b itm aster transmitter microcontroller slavereceiver, frommastertoslave fromslavetomaster www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 21/65 6.1.7 communication flow the communication is managed by the microcontroller that generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. data is transferred as 8-bit bytes, msb first. the first byte following the start condition contains the address (7 bits). a 9 th clock pulse follows the 8 th clock cycle of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. figure 8. i 2 c communication each byte is followed by an acknowledgment bit as indicated by the a or a blocks in the sequence. a start condition immediately followed by a stop condition (void message) is a prohibited format. 6.1.8 i 2 c address each i 2 c connected to the bus is addressable by a unique address. the i 2 c address is 7 bits long, and there is a simple master/slave relationship. the lsb of the L6360 address can be programmed by means of dedicated ic pins (sa0, sa1 and sa2, which can be hard wired to v dd or gnd, or handled by c outputs): the microcontroller can interface up to 8 L6360 ics. the i 2 c inside the device has 5 pins: sda: data scl: clock sa0: lsb of L6360 address sa1: bit 1 of L6360 address sa2: bit 2 of L6360 address www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 22/65 doc id 022817 rev 2 the i 2 c L6360 ic address is: fixed part (4 msbits): set to ?1100? programmable part (3 lsbits) by hardware: from ?000 to 111" connecting sax pins to gnd or v dd . in L6360 the sda is an open drain pin. 6.1.9 internal registers the L6360 has some internal registers to perform control, configuration, and diagnostic operations. these registers are listed below: status register configuration register control register 1 control register 2 led1 register msb led1 register lsb led2 register msb led2 register lsb parity register. each register is addressable: table 12. register addresses address register name 0000 status register 0001 configuration register 0010 control register 1 0011 control register 2 0100 led1 msb 0101 led1 lsb 0110 led2 msb 0111 led2 lsb 1000 parity register www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 23/65 status register read only reset value: [00000000] figure 9. status register the status register stores diagnostic information. it can be read to check the status of the run-time of the device (faults, warning, transmission corrupted, etc.). when a fault condition occurs, a bit (corresponding to the fault condition) in the status register is set and an interrupt (via the irq pin) is generated. if there is no persistent fault condition, the status register is cleared after a successful current read . bit 7 = po : power-on (l+ line) . this bit indicates the status of l+ line voltage. if the voltage goes under the lower threshold (v lt h o f f ) and en l+ is high, the po bit is set. it is reset after a successful current read if the l+ voltage has returned above the upper threshold v lt h o n and the read operation has begun after the bit has been set. when the po bit is high, irq is generated. during en l+ transition (from low-level to high-level) and during l+ line voltage transition, a fault condition is reported setting the po bit and activating the irq pin. to reset the fault a successful current read is necessary. 0/ /64 #1/, ,/, ,. 0% !- 2%' www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 24/65 doc id 022817 rev 2 figure 10. power-on bit behavior bit 6 = not used: always at zero bit 5 = ovt : overtemperature fault this bit indicates the status of the ic internal temperature. if the temperature goes above the thermal shutdown threshold (t > t jsd ) the ovt bit is set. it is reset after a successful current read if the temperature has returned below the thermal restart threshold (t jds - t jhist ) and the read operation has begun after the bit has been set. when ovt bit is high, the power outputs are disabled and irq is generated. figure 11. overtemperature (ovt) bit behavior #urrentread 6 , 6 4(/. 6 4(/&& 0/ 6 ,(934 !- 4 * 4 *3$ 4 *234 /64 4 *(934 #urrentread !- www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 25/65 bit 4 = cqol : c/q overload this bit is set if a cutoff occurs on the c/q channel. it is reset after a successful current read if the restart delay time (t rcoq ) has elapsed or the protection is latched (bit t rcoq = 1 in control register 1 ). the read operation should begin after the cqol bit has been set. see also the control register 1 and transceiver sections. when cqol bit is high, irq is generated. when cqol bit is high and the protection is latched (bit t rcoq = 1 in control register 1 ), the c/q power output is disabled. see figure 12 . figure 12. cutoff behavior 1 t dcoq t rcoq t dcoq t rcoq t dcoq 88 t rcoq t dcoq 88 t rcoq #1/, #1/, ) #/ ) #/ 1 !- #1driverdisabled #1driverdisabled #urrentread #urrentread #ontrol register #ontrol register t t t t www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 26/65 doc id 022817 rev 2 bit 3 = lol : l+ overload this bit is set if a cutoff occurs on the l+ driver. it is reset after a successful current read if the restart delay time (t rcol ) has elapsed or the protection is latched (bit t rcol = 1 in control register 2 ). the read operation should begin after the lol bit has been set. see also the control register 2 and tr a n s c e i ve r sections. when lol bit is high, irq is generated. when lol bit is high and the protection is latched (bit t rcol = 1 in control register 2 ), the l+ power output is disabled. the behavior is the same as the c/q driver (see figure 12 ). bit 2 = not used: always at zero bit 1 = reg ln : linear regulator undervoltage fault this bit is set in case of undervoltage of the linear regulator output (v reglnl ). it is reset after a successful current read if the linear regulator output has returned to normal operation and the read operation has begun after the bit has been set. when reg ln bit is high, irq is generated. bit 0 = pe : parity check erro r this flag is set if parity error occurs. control register 1 read/write reset value: [00100001] figure 13. control register 1 the control register holds the parameters to control the L6360. see also the transceiver section. bit 7 = en cgq : c/q i pull-down enable table 13. en cgq : c/q pull-down enable en cgq pull-down generator status 0always off 1 if en c/q = 0 on if en c/q = 1 off www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 27/65 bit 6:5 = i coq [1:0] : c/q o hs and ls cutoff current this bit is used to configure the cutoff current value on the c/q channel, as shown in ta b l e 1 4 . bit 4:3 = t dcoq [1:0] :c/q o hs and ls cutoff current delay time the channel output driver is turned off after a delay (t dcoq ) programmable by means of these two bits: bit 2 = t rcoq : c/q o restart delay time after a cutoff event, the channel driver automatically restarts after a delay (t rcoq ) programmable by means of this bit: table 14. i coq : c/q o hs and ls cutoff current i coq [1] i coq [0] typ. 0 0 115 ma 0 1 220 ma 1 0 350 ma 1 1 580 ma table 15. t dcoq : c/q o hs and ls cutoff current delay time t dcoq [1] t dcoq [0] typ. 0 0 100 s 0 1 150 s 1 0 200 s 1 1 250 s (1) 1. according to power dissipation at 2 khz switching, c < 1 f, power dissipation 0.7 w. table 16. t rcoq : c/q o restart delay time t rcoq typ. 0 255 x t dcoq 1 latched (1) 1. unlatch through i 2 c communication (reading or writing any internal registers). www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 28/65 doc id 022817 rev 2 bit 1:0 = t dbq [1:0] : c/q i de-bounce time de-bounce time is the minimum time that data must be in a given state after a transition. it is a programmable time, and can be configured as shown in ta b l e 1 7 . control register 2 read/write reset value: [0x100001] figure 14. control register 2 the control register holds the parameters to control the L6360. see also the transceiver section. bit 7 = en cgi : i/q pull-down enable . bit 5 = cq pdg : c/q, channel pull-down generators in order to reduce consumption, it is possible to switch from default to low-power configuration by resetting the cq pdg bit. . table 17. t dbq : c/q i de-bounce time t dbq [1] t dbq [0] typ. 000 s 015 s 1 0 20 s 1 1 100 s table 18. en cgi : i/q pull-down enable en cgi pull-down generator status 0always off 1always on table 19. cq pdg : c/q pull-down generator switching cq pdg pull-down generator status 0i ini/qi (input current c/q i pin) = 2.5 ma 1i inc/qi (input current c/q i pin) = 5.5 ma !- %. #') #1 0$' , #/$ t dcol t rcol t dbi t dbi www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 29/65 bit 4 = l+ cod : l+ cutoff disable the cutoff function on the l+ switch can be enabled or disabled according to the l+ cod bit. as the cutoff function is intended to protect the integrated switches against overload and short-circuit, disabling the cutoff is not recommended. bit 3 = t dcol : l+ cutoff current delay time the channel output driver is turned off after a delay (t dcol ) programmable by means of this bit: bit 2 = t rcol : l+ restart delay time after a cutoff event, the channel driver automatically restarts again after a delay (t rcol ) programmable by means of this bit: bit 1:0 = t dbi [1:0] : i/q de-bounce time de-bounce time is the minimum time that data must be in a given state after a transition. it is a programmable time, and it can be configured as shown in ta b l e 2 3 . table 20. l+ cod : l+ cutoff disable l+ cod l+ cutoff current status 0 enabled 1 disabled table 21. t dcol : l+ hs cutoff current delay time t dcol typ. 0500 s 10 s table 22. t rcol : l+ restart delay t rcol typ. 0 64 ms 1latched (1) 1. unlatch through i 2 c communication (reading or writing any internal registers). table 23. t dbi : i/q de-bounce time t dbi [1] t dbi [0] typ. 000 s 015 s 1 0 20 s 1 1 100 s www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 30/65 doc id 022817 rev 2 configuration register read/write reset value: [100xxxxx] figure 15. configuration register the configuration register holds data to configure the L6360 ic. bit 7:5 = c/q[2:0] : c/q output stage configuration !- #1 #1 # 1 table 24. c/q output stage configuration c/q[2] c/q[1] c/q[0] configuration notes 000 off hs and ls are off regardless of the state of en c/q and in c/q . the receiver is off regardless of the state of en c/q . 0 0 1 low-side hs is always disabled. ls is on when in c/q is high and en c/q is high, off in all other cases. slow asynchronous decay when the ls is turned off by en c/q or in case of cutoff. the receiver is off when en c/q is high: out c/q is high. the receiver is on when en c/q is low: if c/q i is high, out c/q is low. if c/q i is low, out c/q is high. 010high-side ls is always disabled. hs is on when in c/q is low and en c/q is high, off in all other cases. slow asynchronous decay if the hs is turned off by en c/q or in case of cutoff. the internal pull-down current generator on c/q i should be disabled through control register 1 , unless c/q i is connected to c/q o through a 100 (or more) resistor. the receiver is off when en c/q is high: out c/q is high. the receiver is on when en c/q is low: if c/q i is high, out c/q is low. if c/q i is low, out c/q is high. www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 31/65 note: see also the demagnetization section. 011push-pull in c/q low and en c/q high: hs on and ls off. in c/q high and en c/q high: ls on and hs off. if en c/q is low, both hs and ls are off. slow asynchronous decay in case of cutoff or turn-off of both switches. an internal deadtime is generated between each ls turn-off and the following hs turn-on and between each hs turn-off and the following ls turn-on. the receiver is off when en c/q is high: out c/q is high. the receiver is on when en c/q is low: if c/q i is high, out c/q is low. if c/q i is low, out c/q is high. 100tristate hs and ls are off regardless of the state of en c/q and in c/q . the receiver is off when en c/q is high: out c/q is high. the receiver is on when en c/q is low: if c/q i is high, out c/q is low. if c/q i is low, out c/q is high. 101low-side on ls is on regardless of the state of en c/q and in c/q . slow asynchronous decay in case of cutoff. the receiver is off when en c/q is high: out c/q is high the receiver is on when en c/q is low: if c/q i is high, out c/q is low. if c/q i is low, out c/q is high. 1 1 0 high-side on hs is on regardless of the state of en c/q and in c/q . slow asynchronous decay in case of cutoff. the receiver is off when en c/q is high: out c/q is high. the receiver is on when en c/q is low: if c/q i is high, out c/q is low. if c/q i is low, out c/q is high. 111 push-pull inductive load in c/q low and en c/q high: hs on and ls off. in c/q high and en c/q high: ls on and hs off. if en c/q is low, both hs and ls are off. slow asynchronous decay in case of cutoff or turn-off of both switches. an internal deadtime is generated between each ls turn-off and the following hs turn-on and between each hs turn-off and the following ls turn-on. the receiver is off when en c/q is high: out c/q is high. the receiver is on when en c/q is low: if c/q i is high, out c/q is low. if c/q i is low, out c/q is high. table 24. c/q output stage configuration (continued) c/q[2] c/q[1] c/q[0] configuration notes www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 32/65 doc id 022817 rev 2 in order to reduce the risk of damage to the output stage (e.g. switching from push-pull inductive load to any transceiver configuration while an inductive load has some residual energy), the user must not switch between any two ?active? (low-side, high-side, push-pull, low-side on, high-side on, push-pull inductive load) configurations of the bridge. for example, if the microcontroller needs to switch from push-pull to high-side configuration, it needs to modify the configuration register twice: first-step : switch from push-pull to off (or tristate) second-step : switch from off (or tristate) to high-side if the microcontroller asks for a forbidden jump between configurations, the ic remains in the previous configuration and reports a parity error to the microcontroller. in case of sequential write, no parity error is generated if the microcontroller rewrites the configuration register with the previous value; if the operation, instead, requires a forbidden jump, all data are rejected also for other registers (and a parity error is raised). the l+ switch is a high-side switch. hs is on when en l+ is high, otherwise it is off. fast decay with active clamp (-v demag ) is operated when the hs is turned off or in the case of cutoff. receiver i/q is always on. bit 4:2 = not used bit 1:0 = not used led registers see also the diagnostic led sequence generator and driver section. these registers are used to configure the two led drivers integrated in the ic. each led driver has two associated registers and turns on or off the external led according to the information stored in the registers, which are scanned with a rate of 63 ms per bit. led drivers can be used for status or diagnostic information, or for other purposes, and should be configured by the host microcontroller. led1 registers reset value: [00000000] figure 16. led1 registers !- ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 33/65 led2 registers reset value: [00000000] figure 17. led2 registers parity register read only reset value: [00000000] figure 18. parity register this register stores the parity of each register, calculated after the L6360 receives data registers. bit 7 = sr : status register parity this bit is the parity of the status register. bit 6 = cr : configuration register parity this bit is the parity of the configuration register. bit 5 = ct1 : control register 1 parity this bit is the parity of control register 1. bit 4 = ct2 : control register 2 parity this bit is the parity of control register 2. bit 3 = l1h : led1 high register parity this bit is the parity of the led1 msb register (15 down to 8). bit 2 = l1l : led1 low register parity this bit is the parity of the led1 lsb register (7 down to 0). bit 1 = l2h : led2 high register parity this bit is the parity of the led2 msb register (15 down to 8). bit 0 = l2l : led2 low register parity this bit is the parity of the led2 lsb register (7 down to 0). !- ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 34/65 doc id 022817 rev 2 6.1.10 startup defa ult configuration ta b l e 2 5 and ta b l e 2 6 show the device registers default configuration. table 25. parameters default configuration parameter default value i coq 220 ma t dcoq 100 s t rcoq 25 ms t dbq 5 s t dcol 0 s t rcol 64 ms t bdq 5 s output stage tristate table 26. registers default configuration registers bit position bit name reset value status register bit 7 po 0 bit 6 not used x bit 5 ovt 0 bit 4 cqol 0 bit 3 iqol 0 bit 2 not used x bit 1 reg ln 0 bit 0 pe 0 configuration register bit 7 c/q2 1 bit 6 c/q1 0 bit 5 c/q0 0 bit 4 not used x bit 3 not used x bit 2 not used x bit 1 not used x bit 0 not used x www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 35/65 control register 1 bit 7 en cgq 0 bit 6 i coq 10 bit 5 i coq 01 bit 4 t dcoq 10 bit 3 t dcoq 00 bit 2 t rcoq 0 bit 1 t dbq 10 bit 0 t dbq 01 control register 2 bit 7 en cgi 0 bit 6 not used x bit 5 cq pdg 1 bit 4 l+ cod 0 bit 3 t dcoi 00 bit 2 t rcoi 0 bit 1 t dbi 10 bit 0 t dbi 01 led1 register msb bit 7 l1r15 0 bit 6 l1r14 0 bit 5 l1r13 0 bit 4 l1r12 0 bit 3 l1r11 0 bit 2 l1r10 0 bit 1 l1r9 0 bit 0 l1r8 0 led1 register lsb bit 7 l1r7 0 bit 6 l1r6 0 bit 5 l1r5 0 bit 4 l1r4 0 bit 3 l1r3 0 bit 2 l1r2 0 bit 1 l1r1 0 bit 0 l1r0 0 table 26. registers default configuration (continued) registers bit position bit name reset value www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 36/65 doc id 022817 rev 2 6.2 interrupt the irq pin (interrupt pin) should normally be held to a high logic level by an external pull- up resistor or microcontroller pin configuration. the internal structure is an open drain transistor. it should be connected directly to the microcontroller so, in the case of a fault event (c/q overload, power-on l+ line, overtemperature condition, etc.), it is pulled down to a low logic level, reporting the fault condition to the microcontroller. see also the status register section. led2 register msb bit 7 l2r15 0 bit 6 l2r14 0 bit 5 l2r13 0 bit 4 l2r12 0 bit 3 l2r11 0 bit 2 l2r10 0 bit 1 l2r9 0 bit 0 l2r8 0 led2 register lsb bit 7 l2r7 0 bit 6 l2r6 0 bit 5 l2r5 0 bit 4 l2r4 0 bit 3 l2r3 0 bit 2 l2r2 0 bit 1 l2r1 0 bit 0 l2r0 0 parity register bit 7 sr 0 bit 6 cr 0 bit 5 ct1 0 bit 4 ct2 0 bit 3 l1h 0 bit 2 l1l 0 bit 1 l2h 0 bit 0 l2l 0 table 26. registers default configuration (continued) registers bit position bit name reset value www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 37/65 6.3 demagnetization the power stage can be represented as in figure 19 . figure 19. power stage. q2 is not present on l+ output when a power stage output (c/q or l+) is connected to an inductance, the energy stored in the load is: equation 1 this energy must be properly dissipated at the switch-off. without an appropriate circuitry the output voltage would be pulled to very negative values, therefore recovering the stored energy through the power transistor's breakdown. to avoid this, the output voltage must be clamped so that the voltage across the power switch does not exceed its breakdown voltage. in the case of load connected between the c/q o pin and v cc , at switch-off (of the low-side switch) the output is pushed to a voltage higher than v cc . e 1 2 -- - li 2 = www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 38/65 doc id 022817 rev 2 6.3.1 fast demagnetization applies to l+ channel only. figure 20. fast demagnetization principle schematic. load connected to l- when a high-side driver turns off an inductance, a reversed polarity voltage appears across the load. the output pin (l+) of the power switch becomes more negative than the ground until it reaches the demagnetization voltage, v demag . the conduction state of the power switch q1 is linearly modulated by an internal circuitry in order to keep the voltage at c/q or the i/q pin at about v demag until the energy in the load has been dissipated. the energy is dissipated in both ic internal switch and load resistance. figure 21. fast demagnetization waveform. load connected to l- www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 39/65 6.3.2 slow demagnetization applies to c/q channel. figure 22. slow demagnetization schematic block. load connected to l- when a high-side driver turns off an inductance a reversed polarity voltage appears across the load. in slow demagnetization configuration the low-side switch q2 is on and the c/q pin is pulled at a voltage slightly (depending on q2 drop) below the ground (l-). the energy is dissipated in both the ic internal switch and the load resistance. in the case of load connected between the c/q pin and v cc , at switch-off (of the low-side switch q2), the switch q1 is on and the output is pushed to a voltage slightly higher than v cc . figure 23. slow demagnetization waveform. load connected to gnd www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 40/65 doc id 022817 rev 2 6.4 i 2 c protocol 6.4.1 protocol configuration figure 24. device initialization microcontroller initialization : microcontroller initialization phase. write mode : the L6360 is configured by the microcontroller through i 2 c. to configure the device, it is necessary to write its internal registers (see write modes section). parity check : L6360 calculates the parity of each received register and stores it in the parity register. after which, it compares it with the parity transmitted together with the data. if the parity check of one or more registers failed, the ?parity error bit? in the status register is set and an interrupt is generated by the L6360. the microcontroller can now read the status register and the parity register ( current read ). so the microcontroller can understand the interrupt cause and which register failed the transmission. if the parity check is ok, the flow goes on ( read modes ). write register failed : the microcontroller can again write the register(s) that failed the check. read mode : read status register to monitor if the configuration was good ( read modes ). 7rite mod e 0arity ch eck 9 . 2ead mode 2esend fai led registers %xit -icrocontroller in itialization 7521 !- www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 41/65 6.4.2 operating modes write modes the L6360 is configured by the microcontroller through i 2 c. to configure the device, it is necessary to write its internal registers. there are two writing modes: current : single register sequential : all registers in sequence current write mode the microcontroller i 2 c is configured as master transmitter. the L6360 i 2 c is configured as the slave receiver. figure 25. current write mode flow chart procedure . 7rite mode #522%.4 $ataregister transmission 3tartcondition 3topcondition 0arity ch eck %xit 9 0aritycheck !ddress register parity transmission #urrent 2e admode )nterrupt !- sends slaveaddress -icrocontroller www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 42/65 doc id 022817 rev 2 1. microcontroller i 2 c establishes the communication: start condition 2. microcontroller i 2 c sends the slave address on the i 2 c bus to check if the slave is online (1 st frame) 3. after the address is matched, the microcontroller starts the data transmission: the 2 nd frame is the data to be written into the selected register (see 3 rd frame ) 4. the 3 rd frame is composed of the address of the register to be written and of the parity of the 2 nd frame. 5. microcontroller i 2 c finishes the communication: stop condition 6. the L6360 calculates the parity of the data received 7. the L6360 compares its parity calculation with the parity bits in the 3 rd frame (sent by the microcontroller) 8. if the parities match, the protocol flow goes on (exit), otherwise the pe bit inside the L6360 status register is set and the flow goes to the next state. 9. the L6360 generates an interrupt to report the parity check error. 10. the microcontroller sends a read request to the device. the L6360 then sends the status and parity registers. the microcontroller can resend the corrupted data register. 11. back to step 1. the i 2 c frame (configuration, control, diagnostic phases) must provide: slave address (7 bits) transmission direction (read/write) data (8 bits: data register) parity bits (p2, p1, p0) registers address (4 bits: 16 registers addressable) the three frames are shown in figure 26 and below: figure 26. current write mode frames ! !ddress !ddress 2egister 2egister ! ! ! ! ! ! 2 2 2 2 0 0 $ $ $ $ $ $ $ $ 0 $ata $ata nd fr ame nd fr ame rd fr ame rd fr ame st fr ame st fr ame 0arity 0arity $irection $irection 3 0 5nused 5nused 3 0 3tart condition 3top condition !- 7 www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 43/65 1 st frame bit 71: L6360 address bit 0: direction 2 nd frame bit 70: data register 3 rd frame bit 75: parity bits bit 4: unused bit 30: register address the parity check bits are calculated as shown in equation 2 : equation 2 p0 = d7 d6 d5 d4 d3 d2 d1 d0 p1 = d7 d5 d3 d1 (odd parity) p2 = d6 d4 d2 d0 (even parity) if parity error occurs, the register are not overwritten. table 27. current write mode direction bit w bit master slave 0 write mode read mode 1 read mode write mode www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 44/65 doc id 022817 rev 2 sequential write mode figure 27. sequential write mode flow chart procedure 1. the microcontroller i 2 c establishes the communication: start condition. 2. the microcontroller i 2 c sends the slave address on the i 2 c bus to check if the slave is online (1 st frame). 3. after the address is matched, the microcontroller starts the sequential transmission (2 nd 8th frame). 4. the microcontroller sends its parity register (last frame: 9 th frame). 5. microcontroller i 2 c finishes the communication: stop condition. 6. the L6360 calculates the parity of the registers received, and stores the results in the parity register. 7. the L6360 compares its parity register with the parity register sent by the microcontroller (9 th frame). 8. if the parities match, the protocol flow goes on (exit), otherwise the pe bit inside the L6360 status register is set, and the flow goes to the next state. 9. the L6360 generates an interrupt to report the parity check error. 10. the microcontroller sends a read request to the device. in this phase the L6360 sends the status register and the parity register allowing the microcontroller to verify which register failed the configuration. . -icrocontrollersends slaveaddress 7rite mode 3%15%.4)!, 3equential transmission 3tartcondition 3topcondition 0arity check %xit 9 0arityfrom microcontroller #urrent 2eadmode )nterrupt !- .ew transmission -icrocontrollersends slaveaddress 3tart condition www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 45/65 11. now the microcontroller can perform a new write sequential procedure. 12. microcontroller i 2 c establishes the communication: start condition. 13. microcontroller i 2 c sends the slave address on the i 2 c bus to check if the slave is online. 14. the microcontroller resends the data registers. 15. back to step 5. the i 2 c frame (configuration, control, diagnostic phases) must provide: slave address (7 bits) transmission direction (read/write) data (8 bits: data registers) the 9 frames are shown below: figure 28. sequential write mode frames 1 st frame bit 71: L6360 address bit 0: direction (write/read) 3 ! 3 0 3tartcondition 3topcondition ! ! ! ! ! ! 7 $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ st frame nd fr ame th fr ame th fr ame !ddress $ata $irection $ata $ata 0 !- www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 46/65 doc id 022817 rev 2 2 nd 8th frame bit 70: data register 9 th frame bit 70: microcontroller parity register the microcontroller parity check (for each register) calculus performed is shown below: figure 29. microcontroller parity check calculus bit 6 = p6 : microcontroller configuration register parity this bit is the parity of the configuration register. bit 5 = p5 : microcontroller control register 1 parity this bit is the parity of control register 1. bit 4 = p4 : microcontroller control register 2 parity this bit is the parity of control register 2. bit 3 = p3 : microcontroller led1 register high parity this bit is the parity of the led1 msb register (15 down to 8). bit 2 = p2 : microcontroller led1 register low parity this bit is the parity of the led1 lsb register (7 down to 0). bit 1 = p1 : microcontroller led2 register high parity this bit is the parity of the led2 msb register high (15 down to 8). bit 0 = p0 : microcontroller led2 register low parity this bit is the parity of the led2 lsb register high (7 down to 0). for each register, a parity check is calculated as shown in equation 3 , in general formulas: equation 3 px = d7 d6 d5 d4 d3 d2 d1 d0 (x = 0 to 6) d7 d0 indicates bits inside each register. if parity error occurs, the registers are not overwritten. in this writing mode, all writable registers and the microcontroller parity register are sent. table 28. sequential write mode direction bit w master slave 0 write mode read mode 1 read mode write mode 0 0 0 0 0 0 0 !- www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 47/65 figure 30. register sequence in sequential write mode read modes the status register and parity check register are read only. the other registers are readable/writable (by microcontroller). there are three reading modes: current : status register only sequential : all registers in sequence random : to read registers in sequence starting from a register address fixed by the microcontroller. all registers are addressed as shown in ta b l e 3 0 : table 29. read mode: register address address register name 0000 status register 0001 configuration register 0010 control register 1 0011 control register 2 0100 led1 register msb 0101 led1 register lsb 0110 led2 register msb 0111 led2 register lsb 1000 parity register www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 48/65 doc id 022817 rev 2 current read mode figure 31. current read mode flow chart procedure 1. microcontroller i 2 c establishes the communication: start condition 2. microcontroller i 2 c sends slave address on the i 2 c bus to check if the slave is online (1 st frame) 3. after the address is matched, the L6360 sends its status register (2 nd frame) 4. the L6360 sends its parity register (3 rd frame) 5. microcontroller i 2 c finishes the communication: stop condition. the i 2 c frame (configuration, control, diagnostic phases) must provide: slave address (7 bits) transmission direction (read/write) data (8-bit data registers): status and parity registers. !- -icrocontrollersends slaveaddress 2ead mo de #522%.4 da ta register 3tartcondition 3topcondition %xit register 0arity 3tatus www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 49/65 the three frames are shown in figure 32 . figure 32. current read mode frames when a ?read request? comes from the microcontroller (it is configured as master receiver), the ic (slave transmitter) sends the contents of the status and parity registers. figure 33. current read communication flow ! !ddress ! ! ! ! ! ! 2 $ $ $ $ $ $ $ $ 3tatusregister nd fram e st fram e $irection $irection masterwriteslaveread masterreadslavewrite 3 0arityregister rd fram e 3 0 3tartcondition 3top condition 0 $ $ $ $ $ $ $ $ !- .! sto0 -asterreceiver 3lavetransmitter 3endbythemaster 3endbytheslave 3tart 3laveaddress ! $ata !- www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 50/65 doc id 022817 rev 2 sequential/random read modes figure 34. sequential/random read mode 1. random/sequential read mode initialization: microcontroller i 2 c establishes the communication: start condition. 2. microcontroller i 2 c sends the slave address, in write mode, on the i 2 c bus to check if the slave is online (1 st frame). 3. microcontroller i 2 c sends the register address start point, which sets the first register to read in sequence (2 nd frame). 4. microcontroller i 2 c finishes the communication: stop condition. 5. microcontroller i 2 c sends the slave address, in read mode, on the i 2 c bus to check if the slave is online (3 rd frame). 6. after the address is matched, the L6360 sends its registers in sequential mode, starting from the register set in the 2 nd frame. 7. microcontroller i 2 c finishes the communication: stop condition. the i 2 c frame (configuration, control, diagnostic phases) must provide: slave address (7 bits) transmission direction (read/write) data (8-bit data register) -icrocontroller sendsslaveaddress 7r itemode 2ead mode 2!.$/- 3%15%.4)!, 3tartcondition -icrocontrollersends ad dressregister startpoint 3topcondition %xit -icrocontroller sendsslaveaddress 2e admode 3tartcondition 3top condition 2andomsequentialinitialization 3equentialreading !- www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 device configuration doc id 022817 rev 2 51/65 the frames structure is shown in figure 35 : figure 35. sequential/random read communication flow 1 st frame bit 7 1: L6360 address bit 0: direction (write) 2 nd frame bit 7 0: address register starting point ! !ddress ! ! ! ! ! ! 7 $ $ $ $ $ $ $ $ $ata nd frame $irection $irection masterwriteslaveread masterreadslavewrite $ataregister fromregister startpoint rd frame 3 0 3tartcondition 3top condition $ $ $ $ $ $ $ $ ! !ddress ! ! ! ! ! ! 2 $irection $ataregister penultimateregister th frame $ $ $ $ $ $ $ $ st frame n th frame 0arityregister $ $ $ $ $ $ $ $ th frame $irection masterwriteslaveread masterreadslavewrite !- 3 0 3 www.datasheet.net/ datasheet pdf - http://www..co.kr/
device configuration L6360 52/65 doc id 022817 rev 2 3 rd frame bit 7 1: L6360 address bit 0: direction (read) 4 th n th frame bit 70: data register (from address register starting point to penultimate address register) 9 th frame bit 70: parity register (the last register) table 30. address register address register name 0000 status register 0001 configuration register 0010 control register 1 0011 control register 2 0100 led1 register msb 0101 led1 register lsb 0110 led2 register msb 0111 led2 register lsb 1000 parity register www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 physical layer communication doc id 022817 rev 2 53/65 7 physical layer communication the ic transfers the data received (on the in c/q digital input pin) at the c/q o output. the en c/q pin allows the c/q o line to be put into tristate. data received from the line (c/q i and i/q pins) is transferred to the digital output pins out c/q and out i/q . figure 36. block diagram communication mode figure 37. system communication mode !- ). #1 disabled %. #1 /54 #1 ). #1 )# transmits on the line the data received on). #1 )#transmitsonthe linethedatareceived on). #1 )# receives data from the line#1 andprovidesit on/54 #1 /utput stage on #1 isenabled /utput stage on #1 is disabled /utput stage on #1 isenabled 88888888888 !- 8 8 8 8 8 8 8 8 8 8 8 )/ ,inkframe )/ ,inkframe )/ ,inkframe www.datasheet.net/ datasheet pdf - http://www..co.kr/
physical layer communication L6360 54/65 doc id 022817 rev 2 7.1 transceiver output drivers (c/q o and l+) are protected against short-circuit or overcurrent by means of two different functions. one is the current limiting function: output current is linearly limited to i limq/l . the cutoff protection, on the other side, is intended to turn off the drivers when the output current exceeds a (programmable for the c/q o driver) threshold (i col/i ). when the current reaches the (programmed) cutoff value the channel output driver is turned off after a programmable delay (t dcoq/l ). the channel output driver automatically restarts again after a programmable delay time (t rcoq/l ). see figure 38 . figure 38. c/q or l+ channel cutoff protection figure 39. c/q or l+ channel current limitation and cutoff protection with latched restart for cqol/lol bit reset see the related status register section. ) #/1, t dcoql t rcoql t t dcoql t rcoql #1 o or ,driverdisabled t #1/,,/, !- #urrentread t dcoql ) #/1, t t dcoql t rcoql t rcoql #1 o or ,driverdisabled #1/, ,/, t #urrentread ) ,)-1, !- www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 diagnostic led sequence generator and driver doc id 022817 rev 2 55/65 7.2 iec 61131-2 type 1 digital inputs two iec61131-2 type 1 inputs are provided: one is available on c/q i (as per io-link specification to support sio mode) and one on the i/q pin. both are provided with a programmable de-bounce filter (t dbq and t dbi , see ta b l e 1 7 and ta b l e 2 3 ) to prevent false triggering. 8 diagnostic led sequence generator and driver each led indication block can drive, through open drain output, one external led. led drivers can be used for status or diagnostic information, or for other purposes, and should be configured by the host microcontroller. two sequences of 16 bits can be programmed (through i 2 c) to generate user specific sequences; each led driver has two associated registers and turns the external led on or off according to the information stored in the registers, which are scanned at a rate of 63 ms per bit; total sequence time of each led is approximately 1 s. see also the led registers section. figure 40 shows how to wire up the two leds: figure 40. led drivers -icrocontroller ,%$ ,%$ 6 $$ '.$ 2 2 $, $, 6 $$ !- , www.datasheet.net/ datasheet pdf - http://www..co.kr/
linear regulator L6360 56/65 doc id 022817 rev 2 9 linear regulator the L6360 embeds a linear regulator with output voltage selectable (by the sel pin) at 3.3 v or 5 v. the input voltage is v h (see ta bl e 3 ) and the maximum power dissipation is 200 mw. the linear regulator minimum limitation current value is i limlr (see ta b l e 7 ). figure 41. linear regulator the linear regulator cannot be turned off as it is necessary to supply (through v dd pin) internal circuitries. it can also be used to supply external circuitry (e.g. the microcontroller). figure 42. linear regulator principle schematic table 31. linear regulator selection pin sel v dd 0 5 v 2.5% 1 3.3 v 2% 6 ( 3%, 6 $$ n& 6or6 selection !- 6 ( , 6 "' ,imitation ci rcuit 6 $$ 2 2 %. , !- www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 application example doc id 022817 rev 2 57/65 10 application example the io-link master system typically consists of a microcontroller and physical layer and it communicates with an io-link device. the principle connection can be seen in figure 43 . figure 43. application example www.datasheet.net/ datasheet pdf - http://www..co.kr/
emc protection considerations L6360 58/65 doc id 022817 rev 2 11 emc protection considerations depending on final product use and environmental conditions, the master application may require additional protection. 11.1 supply voltage protection in order to avoid overvoltages on a system supply, a voltage suppressor such as transil? can be added. a simple protection diagram example is shown in figure 44 . figure 44. supply voltage protection with uni-directional transil performance of the above mentioned example is limited and does not include reverse polarity protection. it is just a cost-effective solution. a more sophisticated solution can be seen in figure 45 . table 32. supply voltage protection component description part function description d_s supply overvoltage protection works as a primary overvoltage clamp to limit supply line distortions - like surge pulses, oscillations caused by line parasitic parameters (inductance) during plug-in phase, etc. 1500 w is recommended to provide reliable protection, uni- directional type helps to avoid negative stress of the L6360. c_f filtering bulk capacitor an energy buffer for application supply, filters the application supply to avoid high ripple during power driver switching, etc. !- 6 ## '.$ '.$ '.$ 072 $?3 3-4! www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 emc protection considerations doc id 022817 rev 2 59/65 figure 45. refined supply voltage protection the above reference diagram provides an extended level of protection in both polarities as well as the reverse polarity protection. if the v h pin of the L6360 is supplied from a separate power supply or if it is decoupled from the main power supply and blocked by bulk capacitors, an additional circuit may be required to ensure the v h voltage is always lower than (or equal to) the main supply voltage (v cc ). a possible solution with diode is shown in figure 46 . table 33. refined supply voltage protection component description part function description d_pwr primary overvoltage protection works as a primary overvoltage clamp to limit supply line distortions - like surge pulses, oscillations caused by line parasitic parameters (inductance) during plug-in phase, etc. 1500 w is recommended to provide reliable protection, uni- directional type is chosen to cover reverse polarity protection. d_pol reverse polarity protection avoids reverse direction current flow and negative voltage stress of the L6360. its current rating (3 a) is chosen in accordance with the maximum driving capabilities of the L6360 power stages. schottky type is recommended to limit power dissipation (low vf). voltage rating (100 v) comes from negative surge to the supply condition. d_s d_pwr support and io overvoltage protection a) shares a positive surge current with the primary protection and limits the overvoltage amplitude. b) clamps surges applied to the L6360 c/q and l+ lines. c_f filtering bulk capacitor an energy buffer for application supply, filters the application supply to avoid high ripple during power driver switching, etc. !- 6 ## '.$ '.$ '.$ '.$ 072 $?3 3-4! $0/, $?072 3-4#! 3403( www.datasheet.net/ datasheet pdf - http://www..co.kr/
emc protection considerations L6360 60/65 doc id 022817 rev 2 figure 46. v h protection vs. v cc table 34. v h protection component description part function description d_vh vh overvoltage protection v h voltage must be always lower than (or equal to) v cc . even during the powering-up and down of an application. this fact must be taken into consideration if v h is supplied from another source (v cc and v h not connected together), charged capacitors, etc. in some cases a diode placed between v cc and v h may help to avoid this violation. !- '.$ 6 ## 5 %.?, %.?#1 ).?#1 / /54?#1 ) /54?)1 3$! 3#, 3! 3! 3! )21 234 ,%$ ,%$ 6 ## 6 ## , #1 / #1 ) )1 '.$ , '.$ , 6 ( 6 $$ 3%, 2 bias $?6( 6 ( , www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 emc protection considerations doc id 022817 rev 2 61/65 11.2 i/o lines protection figure 47 shows external components (capacitors) suitable for io-link communication - protection level in accordance with specification. figure 47. typical protection in io-link applications !- '.$ 6 ## 5 %.?, %.?#1 ).?#1 / /54?#1 ) /54?)1 3$! 3#, 3! 3! 3! )21 234 ,%$ ,%$ 6 ## 6 ## , #1 / #1 ) )1 '.$ , '.$ , 6 ( 6 $$ 3%, 2 bias , '.$ '.$ '.$ '.$ '.$ #. , #1 )1 , # n& #?)1 p& #?#1 p& #?, n& table 35. typical protection in io-link applications component description part function description c_1 power supply blocking energy buffer for the L6360 supply, makes chip supply voltage stable, limits emi noise. c_i/q, c_c/q, c_l+ filtration capacitors work as a basic protection against fast transient signals like burst or radio-frequency domain applied to the lines. limit voltage spikes frequency spectrum and amplitude. www.datasheet.net/ datasheet pdf - http://www..co.kr/
emc protection considerations L6360 62/65 doc id 022817 rev 2 if an extended protection level is required, the solution seen in figure 48 is recommended. it provides robust protection according to iec61131-2. it is suitable for io-link communication and is backward compatible with sio (standard i/o). it protects the L6360 application against high energy surge pulses according to the iec61000-4-5 standard. all the lines are protected against 2.5 kv surge pulse amplitude in common mode and 1 kv in differential mode considering 42 /0.5 f generator coupling. figure 48. io-link and sio applications extended protection , , #1 )1 !- #1 ) #?#1 p& p& )1 , , n& #1 / 5304 $%% 3403,- $?)1 3403,- + ! 6 6 (3 ,3 , #?, #?)1 2?)1 $?#1 table 36. io-link and sio applications extended protection component description part function description c_i/q, c_c/q, c_l+ filtration capacitors work as a basic protection against fast transient signals like burst or radio-frequency domain applied to the lines. limit voltage spike frequency spectrum and amplitude. d_i/q, d_c/q negative voltage spike suppression schottky diodes with low vf clamp the disturbance applied to the lines in a reverse polarity direction. capable of conducting high surge current pulses to avoid high peak current flow through L6360 pins. r_i/q surge current limitation reduces the current flow in the L6360 - the i/q pin in both polarities when e.g. surge noise is applied to the line. if this resistor is omitted, the i/q line surge immunity is lower. u2 (spt01-335dee) overvoltage protection primary surge protection to avoid overvoltage on the L6360 interface. protects l+ switch against negative voltage pulses. shares current flow of negative surge pulses with the additional schottky diodes on c/q and i/q lines. clamps positive surge pulse amplitude applied to i/q line. www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 package mechanical data doc id 022817 rev 2 63/65 12 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? 2 packages, depending on their level of environmental compliance. ecopack2 specifications, grade definitions and product status are available at: www.st.com . ecopack2 is an st trademark. figure 49. package outline for vfqfpn - 26-lead 3.5 x 5 x 1 mm - 0.50 pitch table 37. mechanical data for vfqfpn - 26-lead 3.5 x 5 x 1 mm - 0.50 pitch (1) (2) (3) 1. vfqfpn stands for thermally enhanced ?very thin fine pitch quad flat package no lead?. 2. very thin profile: 0.80 < a 1.00 mm. 3. all dimensions are in millimeters. symbol dimensions min. typ. max. a 0.80 0.90 1.00 a1 0 0.02 0.05 a2 0.20 b 0.18 0.25 0.30 d3.50 d2 1.90 2.00 2.10 e5.00 e2 3.40 3.50 3.60 e0.50 l 0.30 0.40 0.50 6&1&0. , $ % e , b ! ! $ % ! www.datasheet.net/ datasheet pdf - http://www..co.kr/
revision history L6360 64/65 doc id 022817 rev 2 13 revision history table 38. document revision history date revision changes 12-mar-2012 1 initial release. 15-mar-2012 2 updated e load definition in table 3: absolute maximum ratings . updated figure 36: block diagram communication mode . www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6360 doc id 022817 rev 2 65/65 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com www.datasheet.net/ datasheet pdf - http://www..co.kr/

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